The present invention relates to a method and apparatus for processing frame structured data signals.
Many data transmission systems, particularly telecommunications systems, use frame structured data signals to communicate from node to node within the system. A frame structured data signal comprises one or more data frames, each comprising a plurality of data elements arranged in accordance with a frame structure or protocol. Transmission standards as recommended by, for example, the International Telecommunications Union Telecommunications Standardization Sector (ITU-T), describe protocols based on a framed data structure, such as G.703, E1, E2 and E3, and are used by, for example, Synchronous Digital Hierarchy (SDH) and SONET transmission systems. Bellcore DS1, DS2 and DS3 services also use frame structured data signals.
Data elements within a data frame may have different significances or functions. For example, one or more of the data elements may relate to data traffic or payload, while others may relate to overhead information concerning, for example, error checking or control. For a given frame structure, the significance of each data element is determined by its position within the data frame.
When a frame structured data signal is received by a network node, such as a PSTN (Public Standard Telephone Network) exchange, a router or a multiplexer, the node may be required to perform one or more processing operations on the data signal. The network node must determine the significance of each received data element in order to process it appropriately.
Conventionally, a network node includes a processing apparatus having hardware logic or circuitry for interpreting the frame structure. The circuitry includes modules for processing each type of data element and, as a data frame is received, each successive data element is sent to the appropriate processing module. A problem with this arrangement is inflexibility. The circuitry is dedicated to processing a particular frame structure and in a particular manner. The cost of re-designing the circuitry for a different application, or to upgrade, and manufacturing new hardware, typically in the form of an ASIC, is prohibitive. Also, hardware circuitry must be subjected to relatively lengthy testing before being released commercially. Typically, the testing of a conventional hardware implementation as outlined above can account for 60% of the time-to-market of the resulting commercial product.
An alternative is to use a programmable data processor, such as a DSP or RISC processor, to interpret and process a frame structured data signal in software. While this introduces a relatively high level of flexibility, the data processor must keep track of the position of each data element within each data frame. The processing power required to do this is relatively high. For a given VLSI device area or gate count, the speed at which a data processor can process a frame structured data signal is significantly less than a corresponding hardware implementation. In many applications, therefore, a data processor which interprets frame structure in software is unsuitable, that is, too inefficient, for processing a frame structured data signal in real time.
Accordingly, a first aspect of the invention provides an apparatus for processing a frame structured data signal, the data signal comprising at least one data frame comprising a plurality of data elements arranged in accordance with a frame structure, the apparatus comprising: a data frame detector module, arranged to receive the data signal and to generate a frame detect signal upon detection of a data frame;
a tag generating module, responsive to said frame detect signal and to said data signal, and arranged to generate a tag element for each data element, the configuration of the tag element corresponding to the position of the respective data element within the detected data frame; and
a data element processor, arranged to perform one or more respective processing operations relating to one or more of said data elements,
wherein the or each processing operation to be performed for a data element is determined by the configuration of the respective tag element.
Associating a tag element with each data element removes the need for the data processor to keep track of the position of each data element in its respective data framexe2x80x94the data processor does not need to calculate the position, and therefore significance, of each data element within its respective frame since this information is identified by the configuration of the respective tag element. This significantly increases the speed at which the data processor can process a frame structured data signal. The apparatus of the invention thus enjoys the flexibility afforded by a data processor while having relatively low processing power requirements. As a result, the apparatus is capable of processing a relatively high volume of data in real time, and is programmable to support more than one frame structure and data rate thereby reducing development, implementation, field maintenance and upgrade costs.
Preferably, the tag generating module includes a data element counter, responsive to the frame detect signal and to the data signal, and arranged to count the number of data elements detected after the detection of a data frame; and an encoder module, co-operable with the data element counter to generate a tag element for each data element, the configuration of the tag element depending on the number of data elements counted since the detection of said data frame.
Preferably, the apparatus further includes a data buffer and is arranged such that each data element is stored in the data buffer in association with a respective tag element.
Advantageously, the data processor is co-operable with a program memory, the program memory being programmable with a plurality of processing modules, each processing module defining one or more processing operation, wherein the configuration of one or more tag element identifies a respective location in said program memory corresponding with one or more processing modules to be executed, by said data processor, in relation to a respective data element. Preferably, one or more data elements are processed within an interrupt service routine, each respective tag element corresponding with a respective tag handler for identifying a respective processing module.
Advantageously, the apparatus further comprises a data element aligner, responsive to the frame detect signal and to the data signal, and arranged to provide each data element in parallel, the data element aligner being co-operable with the tag generating module so that each parallely provided data element is generated in synchronism with a respective tag element.
A second aspect of the invention provides a method of processing a frame structured data signal, the data signal comprising at least one data frame comprising a plurality of data elements arranged in accordance with a frame structure, the method comprising: receiving the data signal; generating a frame detect signal upon detection of a data frame; generating a tag element for each data element, the configuration of the tag element corresponding to the position of the respective data element within the detected data frame; and performing one or more respective processing operations relating to one or more of said data elements, wherein the or each processing operation to be performed for a data element is determined by the configuration of the respective tag element.
Preferably, the method further includes counting the number of data elements detected after the detection of a data frame; and generating a tag element for each data element, the configuration of the tag element depending on the number of data elements counted since the detection of said data frame.
Advantageously, the method further includes storing each data element in a data buffer in association with a respective tag element.
Preferably, the method further includes programming a program memory with a plurality of processing modules, each processing module defining one or more processing operation; and executing one or more processing module in relation to a respective data element, wherein the configuration of one or more tag element identifies a respective location in said program memory corresponding with one or more processing modules to be executed in relation to said respective data element.
Preferably, the method further includes aligning the data signal to provide each data element in parallel; and synchronizing the generation of each tag element with a respective parallel data element.
Other aspects of the invention will become apparent to those ordinary skilled in the art upon review of the following description of specific embodiments of the invention and with reference to the accompanying drawings.